The present invention relates to a manufacturing technique for a semiconductor device and to, e.g., a technique which is effective when applied to a manufacturing technique for a semiconductor device in which a nonvolatile memory is embedded as an add-on circuit which is added to a main circuit including a field effect transistor.
In a semiconductor device formed with a main circuit including a MISFET (Metal Insulator Semiconductor Field Effect Transistor) as a field effect transistor, an additional circuit (add-on circuit) which is added to the main circuit may be formed separately from the main circuit which provides the main function of the semiconductor device. Examples of the additional circuit include an electronic fuse used for the trimming or relief of the main circuit and a memory which stores trimming information.
In recent years, there has been a growing need for an MTP (Multi Time Programmable) electronic fuse which uses a rewritable nonvolatile memory and can be adjusted many times. At present, as a memory which stores trimming information, a nonvolatile memory (NV memory) having a floating gate structure, which is appropriate for being embedded together with the field effect transistor included in a main circuit, is used. However, this increases the size of a memory cell and therefore a change to a nonvolatile memory which allows a reduction in the size of a memory cell is under consideration. In view of such a situation, in recent years, it has been considered to use a nonvolatile memory having a MONOS (Metal Oxide Nitride Oxide Semiconductor) structure as an additional circuit.
Each of US Patent Application Publication No. 2007/0102754 (Patent Document 1) and Japanese Unexamined Patent Publication No. 2002-324860 (Patent Document 2) discloses a technique which forms a nonvolatile memory element in a cell array region and forms a MISFET in a peripheral circuit region.
US Patent Application Publication No. 2008/0296664 (Patent Document 3) discloses a technique which forms a nonvolatile charge-trapping memory element in a first region and forms a logic element in a second region. US Patent Application Publication No. 2008/0150002 (Patent Document 4) discloses a technique which forms a SONOS (Silicon Oxide Nitride Oxide Semiconductor) transistor and a MISFET. International Publication No. WO 2013/149669 (Patent Document 5) discloses a technique which produces a tunnel oxide layer for a semiconductor storage device.